This invention relates to a transmitter and a receiver for performing data transmission via a data communication path, and more particularly to an encoder/decoder capable of suppressing an occurrence of an error in a receiver in optical phase shift keying modulated transmission.
In the field of optical transmission, binary phase shift keying (BPSK) is predominantly used, in which 1 bit of information is transmitted per symbol. According to BPSK, to meet the need for increasing transmission capacity, there has been no other way than to decrease a time per symbol, which makes it difficult to increase the transmission speed. In view of this, in order to increase the transmission capacity, there has been developed various transmission methods to increase an amount of information per 1 symbol. Examples of the methods include quadrature phase shift keying (QPSK) and n-ary amplitude shift keying (nASK).
The quadrature phase shift keying (QPSK) modulated transmission is an example of optical many valued phase shift keying modulated transmission. Also, QPSK modulated transmission is a transmission method in which, signal points (P1, P2, P3, and P4) are arranged at phase intervals of π/2 radian in one cycle (2π radian) of the same amplitude and carrier on a complex plane I-Q indicating signals corresponding to 1 symbol (see, OFC/NFOEC 2006, PDP36, 100 Gbit/s DQPSK Transmission Experiment without OTDM for 100G Ethernet Transport, hereinafter referred to as Non-Patent Document 1). The implementation of higher-order PSK has also been devised, as 8-ary phase shift keying (8PSK) modulation and 16-ary phase shift keying (16PSK) modulation.
In the optical transmission including the above-mentioned optical many valued transmission, data to be transmitted is generally subjected to transmission coding. Through the transmission coding, the appearance frequencies of 0 and 1 are made equal, to thereby achieve DC balance and limit the number of successive bits to a finite number (limited run length constraint), which leads to an advantage of, for example, suppressing deterioration in signal quality on the transmission path. For example, as a data transmission technology using a communication interface or a high-speed serial interface in a network device or in a personal computer, U.S. Pat. No. 4,486,739 (hereinafter, referred to as Patent Document 1) discloses a technology using an 8B/10B transmission code. According to the technology, when input serial data is indefinite in appearance frequency of 0 and 1 in number of successive bits, the data is partitioned into units of 8 bits so as to make the appearance frequencies of 0 and 1 equal to each other at relatively short bit intervals (several tens of bits) while limiting the number of successive bits to 5 at maximum.
Alternatively, IEEE Std 802.3-2005, Clause 49 (hereinafter, referred to as Non-patent Document 2) discloses, as another transmission code different from the above, the application of a 64B/66B transmission code. According to the technology, input serial data is partitioned into units of 64 bits, and each 64 bits of data is provided with 2 bits of header information while the 64 bits of data other than the header information is scrambled, to thereby make the appearance frequencies of 0 and 1 stochastically equal to each other, which makes it possible to achieve DC balance on a transmission path. Further, the 2 bits of header information only include “01” and “10” so as to limit the successive equivalent bits to a finite number.